- cross-posted to:
- programmer_humor@programming.dev
- cross-posted to:
- programmer_humor@programming.dev
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If you’re programming in assembly, regardless of what it is, you are the biggest nerd of them all. And I have massive fucking respect for you.
Wow I’m an old engineer nerd. I feel so exposed. Zero is nothing always start at one for life.
What is HTML doing here? Blasphemy!
how dare you Im not an engineer
How is your favourite language one that indexes arrays from 1??? You monster!
How dare you count things from one, like a human being.
I beg to disagree. It’s a law of nature to assign index 0 to the 1st th… Wait a moment
What language is that engineer and a nerd one?
Matlab.
Where holyC
You are a christian nerd
Aww I guess i’m fine since i mainly write in BBC BASIC SDL lol
Neeerd
Have you come to 2025 in a time machine? Can I borrow it?
Sorry I’m using it at the moment doing research for a Roman trading game I’m writing in BASIC.
I am not in this chart because my favourite programming languages are too nerdy for the cool programming nerds to include in their nerd chart.
Super nerd
Turbo Nerd
Same here.
VHDL represent. Although it’s arguably not a “programming language”
You work at IBM or something? Who even still uses VHDL?
A ton of people. Anything aerospace, DoD, Space, or critical infrastructure. All those industries have to use VHDL to support legacy products from the 80s and 90s. At that point everyone is like, “Sure its 2025, by why switch to SystemVerilog? We already know VHDL.” and thus you got a whole army of engineers making next gen satellites, augmented reality headsets, etc. …… in VHDL 93.
Is it such a hassle learning verilog if you know vhdl or vice versa?
Not really, HDL is HDL. At the end of the day, as long as you know what you want to do electrically then everything else is an exercise of translating that desire into VHDL, Verilog, or SystemVerilog. The only real hassle is creating test-benches and verification simulations. But at that point it’s discretionary towards the designer. A lot of tools coming from Intel, Xilinx, and Synopsys allow you to “black box” components. So a module written in VHDL can be incorporated into a design or test bench written in verilog and vis-versa. IMHO VHDL is still dominant because grey beard chief engineers throw a little hissy fit at design reviews when they learn the junior engineers did everything in verilog.
Lol, so much of the FPGA industry 🤣. Especially East coast of the US
you get out of here with your hardware descriptions!
Therefore I can conclude I am not a nerd
I don’t think that’s how it works.
Nerd.
Fair.
Laughs in perl
TMTOWTDI.
Nerd.
R
We can reject the null hypothesis that you are not a nerd at significance $\alpha < 0.001$.
oh wait, shit let me run that again, my data frame is full of NA somehow, again.
what about BASIC
🤓
What is the bottom right language?
Perl. It was the cool thing from 1998 to 2008.
Still the linux sysadmin’s language of choice!
…but some nerds are more equal than others.
Cobol: you are old, and a nerd, and probably making some sweet cheddar right now propping up a mid to late 20th century beast somewhere.
Assembly: you are a cyborg.
Assembly: you are a cyborg.
Or programming a tiny microcontroller to blink a led as efficient as possible.
Something wrong with:
#include <Arduino.h> void loop() { digitalWrite(13, HIGH); delay(1000); digitalWrite(13, LOW); delay(1000); }? 😂🤮
Obviously the only correct way to blink an LED is to use a hardware timer to trigger a DMA transfer which stores a bit in the pin toggle register at a set interval
yeah! Or or use the interrupt pins and a 555 timer! both options are better than python though at least.
